The company has also demonstrated vertical stacking of memory on 28nm logic device for mobile applications. The tapeout plan is to validate HBM on CoWoS. TSMC has demonstrated Wide I/O DRAM - that’s JEDEC standard for Wide I/O 2 for High Bandwidth Memory (HBM) - using CoWoS. The advantage of this, he says, is that the dies on top don’t need TSV processing. He also talked about the CoWoS process (chip on wafer on substrate), where die are placed horizontally on top of the interposer. He talked about a 3D IC design paradigm TSMC calls “through transistor stack” using TSVs to enable heterogeneous vertical scaling. They have a robust More than Moore portfolio with leading-edge 3D transistors.
Ieong’s keynote was titled “A New Paradigm – System Scaling through 3D System Integration.” His message – TSMC has always been an innovator in materials and a leader in providing higher performance technologies. Whatever it takes to stay at the top of the heap. They will provide end-to-end services, or will collaborate with OSAT partners. Heck, they’ll even give them fan-out wafer level packages (FoWLP). According to Mei Kei Ieong, VP Technology, TSMC Europe, the company knows that the end of traditional CMOS scaling is imminent, and as they are in the business of selling wafers, if the customer calls for 3D ICs, they’re going to give them 3D ICs. TSMC clearly sees the writing on the scaling wall. The overarching point is, all of these will coexist and serve the diverse needs of customers. But they’re also all smart enough to not put all their eggs in one basket, and all of them talked about different offerings to address latest design requirements. It’s been established that the manufacturers have everything they need in place to start running product when the system architects start designing in 3D devices. Overall, I would say the key takeaways from this conference at the highest level concerned manufacturing readiness (we are, except for thermal management), cost-of-ownership (we’re working on it and there is progress in these areas) and how much longer is it going to take (this depends on your definition of IT.) The next “killer app” will be wearable devices and the Internet of Things. He also said that as we move to the 10nm node, TSV becomes a required technology for system design.
In his Supply Chain Market Forecast, Mark Stromberg, Principal Analyst Gartner, noted that the economic concerns that are limiting the TSV ramp should be resolved by late 2014-2015, but thinks the number of companies that will implement TSV technology will be limited due to capital costs issues and “macro-based concerns.” I’m not sure I agree with that prediction, but only time will tell. Overall the market forecasts really didn’t reveal anything earth-shatteringly new. So let me start off with some key take-aways and general observations. Three days, 332 attendees from 21 countries, 24 presentations, 3 keynote speakers, 2 panel discussions, several face-to-face interviews and lots of side conversation all about 3D TSVS being Application Ready leads to a good deal of information to process and write about. I just boarded my flight home after attending the 2014 European 3D TSV Summit.
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